Plasma immersion ion implantation is performed by generating a plasma containing ions of species to be implanted in a semiconductor wafer or workpiece. The plasma may be generated using a plasma source, such as a toroidal plasma source, at the reactor chamber ceiling. Ion energy sufficient to achieve an intended ion implantation depth profile below the wafer surface is provided by coupling a very high RF bias voltage (e.g., 10 kV to 20 kV) to the semiconductor wafer through an insulated cathode electrode within the wafer support pedestal. High implant dose rate requires a high plasma ion density, achieved using a toroidal plasma source operating at a low chamber pressure. The requisite ion implant depth profile requires a very high ion energy, achieved by applying a very high RF bias voltage across the plasma sheath at the wafer surface. The process gas employed in plasma immersion ion implantation can be a fluoride or a hydride of the dopant species to be implanted.
In DRAM/flash memory fabrication, implanting a semiconductor dopant species into the polycrystalline silicon (polysilicon) gate electrodes beneficially increases conductivity. The gate electrodes are formed by depositing amorphous silicon on a thin gate oxide layer and then annealing the wafer sufficiently to transform the deposited silicon from the amorphous state to a polycrystalline state. The polycrystalline silicon gate layer thus formed is about 50 nm to 80 nm thick. The implanted species is one promoting p-type conductivity in silicon, such as boron, or n-type conductivity, such as arsenic, phosphorous or antimony. The gate electrode can also be made by certain metals such as TiN or W.
Long refresh time in DRAM is influential for device function. Refresh time is directly proportional to the amount of time charge can be held in DRAM cells. Thus, minimizing the cell junction leakage increases the charge retention time. Gate induced drain leakage (GIDL) is the primary mechanism for junction leakage. Thickening the gate oxide layer at the location of maximum GIDL will reduce overall junction leakage and increase charge retention time.
On the other hand, the layer thickness of the gate oxide continues to be reduced in order to provide suitable gate control over the sub-threshold region. Also, increasing doping density in the channel and source/drain regions advantageously improves punch through characteristics and increase drives. Thus, difficulties exist in providing a scaled down semiconductor device having a suitable balance between high current driving capability and low GIDL current.